000			01569cam a2200325 a 4500
001			35288
003			DLC
005			20240430145126.0
008			090701s2010 nyua b 001 0 eng
010			_a 2009025686
020			_a9780521769921 : _c92.00
020			_a0521769922 : _c92.00
050	0	0	_aQA76.5 _b.B227 2010
090			_aQA 76.5 .B227 2010
100	1		_aBaer, Jean-Loup. _978668
245	1	0	_aMicroprocessor architecture : _bfrom simple pipelines to chip multiprocessors / _cJean-Loup Baer.
260			_aNew York : _bCambridge University Press, _c2010.
300			_axiv, 367 p. : _bill. ; _c26 cm.
505	0		_a1. Introduction; 2. The basics; 3. Superscalar processors; 4. Front-end: branch prediction, instruction fetching, and register renaming; 5. Back-end: instruction scheduling, memory access instructions, and clusters; 6. The cache hierarchy; 7. Multiprocessors; 8. Multithreading and (chip) multiprocessors; 9. Current limitations and future challenges.
520			_aThis book describes the architecture of microprocessors from simple in-order short pipeline designs to out-of-order superscalars.
504			_aIncludes bibliographical references (p. 351-360) and index.
650		0	_aMicroprocessors. _9119027
650		0	_aComputer architecture. _9119030
852	1		_9P92.00usd
907			_a35288 _b04-10-12 _c04-08-12
942			_cBOOK _00
998			_aaudmc _b04-08-12 _cm _da _e- _feng _gnyu _h0
945			_g0 _i5062166 _j0 _laudmc _o- _p338.10 _q- _r- _s- _t1 _u0 _v0 _w0 _x0 _yi13101717 _z04-08-12
999			_c35288 _d35288